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    • 专利摘要:
    26 Abstract En halvledaranordning innefattar ett halvledarchip sammanfogat med ett substrat(122) och en grundplatta sammanfogad med substratet (122). Grundplattan innefattar ettförsta metallskikt (108) beklätt på ett andra metallskikt (106). Det andra metallskiktet (106) ärdeformerat till att bilda en kylstruktur (112) med nålflänsar eller flänsar. Det andra metall-skiktet (106) har ett underskikt (113) som saknar nålar och nålflänsar. Det första metallskiktet(108) har en första tjocklek (d108), och underskiktet (113) har en andra tjocklek (d113).Förhållandet mellan den första tjockleken (d108) och den andra tjockleken (d113) är minst4 : 1. Figur s
    公开号:SE537969C2
    申请号:SE1251008
    申请日:2012-09-10
    公开日:2015-12-22
    发明作者:Olaf Hohlfeld；Andreas Lenniger；Andre Uhlemann
    申请人:Infineon Technologies Ag；
    IPC主号:
    专利说明:

    Title Semiconductor device with coated base plate Background Power electronics modules are semiconductor packages used in power electronics circuits. Power electronics modules are generally used in vehicles and in industry, as well as in inverters and rectifiers. The semiconductor components included in the power electronics modules are usually semiconductor chips with bipolar transistors with insulated control (IGBT) or semiconductor chips with field effect transistors with metal oxide semiconductors (MOSFET). The IGBT and MOSFET semiconductor chips have varying voltage and current values. The semiconductor components included in the power electronics modules may also include diodes, thyristors, field effect transmitters with switching control (JFET) and bipolar transistors. Both passive components and control electronics are not available in the power electronics modules. The semiconductor components are made of Si, SiC, GaN, GaAs or other suitable substrates. Some power electronics modules include additional semiconductor diodes (ie protection diodes) in the semiconductor package for overvoltage protection.
    In general, two different designs of power electronics modules are used. One design is intended for high power applications and the other design for low power applications. For higher power applications, a power electronics module typically includes multiple semiconductor chips integrated on a single substrate. The substrate usually comprises an insulating ceramic substrate, such as Al 2 O 3, AlN, Si 3 N 4 or some other suitable material, to insulate the power electronics module. At least the top of the ceramic substrate is metal coated with either pure or plated Cu, Al or other suitable material to provide electrical and mechanical contacts for the semiconductor chips. The metal layer is generally bonded to the ceramic substrate using a direct copper bonding (DCB) process, a direct aluminum bonding process (DAB) or an active metal brazing (AMB) process. As a rule, soft soldering with Sn-Pb, Sn-Ag, Sn-Ag-Cu or any other suitable solder alloy is used to join a semiconductor chip with a metal-coated ceramic substrate. As a rule, several substrates are combined on a flat base plate of metal !. In this case, the back of the plate is also metal coated with either pure or plated Cu, Al or some other suitable material to join the substrates with the flat base plate of metal !. To join the substrates with the flat base plate of metal, soft soldering with Sn-Pb, Sn-Ag, Sn-Ag-Cu or some other suitable solder alloy is usually used. The flat base plate of metal can in turn be attached to a cooling element, through which a coolant can flow to prevent overheating of the power electronics module during work. 1 With the growing desire to use power electronics in unusual environments (eg in cars) and the ongoing integration of semiconductor chips, the heat dissipated externally and internally continues to drive. There is therefore an increasing demand for power electronics modules for high temperatures that can operate at internal and external temperatures of up to and above 200 ° C. Furthermore, the current density of power electronics continues to increase, leading to an increase in the density of power losses. Water cooling of the power electronics via cooling elements to prevent overheating is therefore becoming increasingly important.
    For these and other reasons, there is a need for the present invention.
    Summary An embodiment provides a semiconductor device. The semiconductor device comprises a semiconductor chip joined to a substrate and a base plate joined to the substrate. The base plate comprises a first metal layer coated on a second metal layer. The second metal layer is deformed to form a squeegee or heat sink structure. The second metal layer has a sublayer that does not have any needles or squeegee flanges. The first metal has a first thickness, and the lower layer has a second thickness. The ratio between the first thickness and the second thickness Or at least 4: 1.
    Brief Description of the Drawings The accompanying drawings are intended to provide a better understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily apparent when the first ones are better by reference to the following detailed description. The elements in the drawings are not necessarily scalable inboard. The same reference numerals denote corresponding and similar parts.
    Figure 1 illustrates a cross-sectional view of a Figure 2 illustrates a cross-sectional view of a coated bimetal strip).
    Figure 3 illustrates a cross-sectional view of a clad trim metal strip).
    Figure 4 illustrates a cross-sectional view of a cooling structure.
    Figure illustrates a cross-sectional view including a cooling structure. embodiment of a semiconductor device. embodiment of a bimetallic strip (i.e. an embodiment of a trimetallic strip (i.e. an embodiment of a base plate which inside another embodiment of a base plate which 2 Figure 6 illustrates a cross-sectional view of an embodiment of a substrate assembly. Figure 7 illustrates a cross-sectional view of an embodiment). of substrate assemblies joined to a base plate.
    Figure 8 illustrates a cross-sectional view of another embodiment of substrate assemblies joined to a base plate.
    Figure 9 illustrates a cross-sectional view of an embodiment of the substrate assemblies, base plate, terminals and frame.
    Figure illustrates a cross-sectional view of an embodiment of the substrate assemblies, base plate, terminals, frame and encapsulation material.
    Figure 11 illustrates a cross-sectional view of an embodiment of the substrate assemblies, base plate, terminals, frame, encapsulation material, and lid.
    Figure 12 illustrates a cross-sectional view of an embodiment of a semiconductor device that includes a chamber for receiving a coolant.
    Figure 13 illustrates a cross-sectional view of another embodiment of a semiconductor device that includes a chamber for receiving a coolant.
    Figure 14 illustrates a perspective view of another embodiment of a semiconductor device.
    Figure illustrates a perspective view of another embodiment of a semiconductor device.
    Figure 16 is a flow chart illustrating an embodiment of a method of manufacturing a semiconductor device.
    Detailed Description In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which, for illustrative purposes, show specific embodiments according to which the invention may be practiced. In this context, terms for directions are used, such as "top", "bottom", "front", "rear", "front", "last", with reference to the direction in the figure or figures described. Since the components within the embodiments can be placed in a number of different directions, the terms for directions for illuminating elements are used and Or is not in any way limiting. Markas should be capable of other embodiments and structural or logical changes are made without departing from the scope of this specification. Thus, the following detailed description is not to be construed as limiting, and the scope of the present invention is defined by the appended claims.
    It should be noted that the properties of the various examples of embodiments described herein may be combined, unless otherwise specifically indicated. The term "electrically coupled" does not mean that the elements must be directly interconnected, but intermediate elements can be provided between the "electrically coupled" elements.
    Figure 1 illustrates a cross-sectional view of an embodiment of a semiconductor device 100. In one embodiment, the semiconductor device 100 is a strong power electronics module for high temperatures (eg, up to and above 200 ° C). The power electronics module 100 includes a chamber 102 for receiving a coolant, a base plate 104, joints 118, substrate assemblies 132a and 132b, a frame 134, terminals 136, encapsulation material 138 and a lid 140. Each substrate assembly 132a and 132b includes metal coated ceramic substrates 122 which includes metal surfaces or layers 120 and 124, joints 126, semiconductor chips 128, and interconnecting wires 130.
    The base plate 104 comprises first metal layer 108 and a second metal layer 106. The first metal layer 108 and the second metal layer 106 consist of different materials. by an embodiment Or the first metal layer 108 after a copper layer or a layer of a copper alloy, and the second metal layer 106 Or an aluminum layer or a layer of an aluminum alloy. In other embodiments, the first metal layer 108 and the second metal layer 106 consist of other suitable materials. In one embodiment, the base plate 104 also includes a third metal layer 110 opposite the second metal layer 106. The third metal layer 110 and the first metal layer 108 are composed of different materials. In one embodiment, the third metal layer 110 is an aluminum layer or a layer of an aluminum alloy. In other embodiments, the third metal layer 110 is a silver layer, a layer of a silver alloy, a palladium layer, a layer of a palladium alloy or a layer of some other suitable material. The first metal layer 108 is lined on the second metal layer 106. The third metal layer 110 is lined on the first metal layer 108. The second metal layer 106 is structured to provide squeegee flanges or flanges 112 and spaces 114 between the squeegee lances or flanges 112.
    The base plate 104 consists of a bimetallic or trimetallic strip (i.e., a coated strip). The base plate 104 provides an inexpensive base plate which can be soldered on one side to follow the first metal layer. In addition, the base plate 104 comprises cooling flanges or needles on the other side, which are combinable with a cooling liquid to follow the second metal layer.
    The chamber 102 for receiving a coolant comprises an inlet 142 and an outlet 144 for guiding a coolant through spaces 114 between the squeegee flanges or flanges 112 in the base plate 104. The chamber 102 is joined to the base plate 104 via screws 116. In other embodiments no screws are used. 116, without the chamber 102 Or glued or laser soldered to the base plate 104. Each substrate assembly 132a and 132b Or joined to the base plate 104 via joints 118. The joints 118 Or soft soldered joints, sintered joints, diffusion soldered joints or other suitable joints. The ceramic substrates 122 comprise Al 2 O 3, AlN, Si 3 N 4 or any other suitable material. In one embodiment, the ceramic substrates 122 each have a thickness of 0.2 to 2.0 mm. The metal layers 120 and 124 comprise Cu, Al or some other suitable material. In one embodiment, the metal layers 120 and / or 124 are plated with one or more layers of Ni, Ag, Au or Pd. In one embodiment, the metal layers 120 and 124 each have a thickness of 0.1 to 0.6 mm. In one embodiment, the metal layers 120 and 124 are bonded to the ceramic substrate 122 using a direct copper bonding (DCB) process to give a DCB substrate, a direct aluminum bonding (DAB) process to give a DAB substrate, or an active metal brazing (AMB) process to provide an AMB substrate. Joints 126 connect the metal layers 124 with semiconductor chips 128. The joints 126 are soft soldered joints, sintered joints, diffusion soldered joints or other suitable joints. The semiconductor chips 128 are electrically connected to the metal layers 124 via interconnecting wires 130. In one embodiment, the semiconductor chips 128 are semiconductor chips that may include IGBT, MOSFET, JFET, bipolar transistors, thyristors, diodes, and / or other lamp power components. The interconnecting wires 130 include Al, Cu, Al-Mg, Au or any other suitable material. In one embodiment, the interconnecting wires 130 are interconnected with semiconductor chips 128 and metal layers 124 using ultrasonic wiring. The metal layers 124 and / or the semiconductor chips 128 are electrically connected to the terminals 136. The terminals 136 extend through the frame 134 to provide external electrical connections to the power electronics module 100 for both power and control connections.
    The frame 134 encloses the joints 118, the substrate assemblies 132a and 132b, the connecting wires 130 and parts of the terminals 136. The frame 134 comprises technical plastic or some other suitable material. The frame 134 is joined to the base plate 104 by screwing, gluing, clamping, soldering or any other suitable method. Encapsulating material 138 fills the areas within the frame 134 around the joints 118, the substrate assemblies 132a and 132b, the interconnecting wires 130 and the portions of the terminals 136. The encapsulating material 138 comprises silicone gel, a silicone coating, a polyimide coating, an epoxy or other coating. materials to provide electrical insulation. The encapsulation material 138 prevents damage to the power electronics module 100 due to dielectric breakdown. The lid 140 is attached to the frame 134 to thank the substrate assemblies 132a and 132b and the encapsulation 138. In one embodiment, the lid 140 is a second encapsulating layer, such as epoxy or some other suitable cover material. In another embodiment, the lid 104 is a tacking device which is attached to the frame 134 by snapping, soldering, gluing or any other suitable method.
    The following Figures 2 to 13 illustrate a method of manufacturing a semiconductor device, such as the semiconductor device 100 previously described and illustrated with reference to Figure 1.
    Figure 2 illustrates a cross-sectional view of an embodiment of a bimetallic strip (i.e., a coated bimetal strip) 200a. The bimetallic strip 200a comprises a first metal layer 108 and a second metal layer 107. The first metal layer 108 and the second metal layer 107 are different materials. In one embodiment, the first metal layer 108 consists of a solderable material which at 20 ° C has a coefficient of thermal expansion (CTE) of less than 18 ppm / K. The second metal layer 107 is selected so that it can be easily machined (eg formed, trimmed and rounded). In one embodiment, the second metal layer 107 is chemically compatible with aluminum in coolant circuits. In one embodiment, the first metal layer 108 is a copper layer or a layer of a copper alloy, and the second metal layer 107 is an aluminum layer or a layer of an aluminum alloy. In other embodiments, the first metal layer 108 and the second metal layer 107 are other lampable metals. In one embodiment, the total thickness of the bimetallic strip 200a is between 5 mm and 6 mm. In one embodiment, the thickness of the first metal layer 108 is equal to the thickness of the second metal layer 107. In one embodiment, the thickness of the first metal layer 108 is between 2.5 mm and 3 mm, and the thickness of the second metal layer 107 is between 2 mm. 5 mm and 3 mm. In another embodiment, the thickness of the first metal layer 108 is between 2.5 mm and 10 mm, and the thickness of the second metal layer 107 is between 2.5 mm and 10 mm. In other embodiments, the thickness of the first metal layer 108 and the thickness of the second metal layer 107 have a second value suitable for obtaining a base plate.
    The first metal layer 108 is coated on the second metal layer 107. In one embodiment, the first metal layer 108 is coated on the second metal layer 107 by bringing the separate layers together in the rollers in a cladding stand. Uniform pressure from the rollers compresses the individual layers and provides a bond between the contact surfaces. The bonded layers were then subjected to recrystallization, tempering and rolling to the final size. After rolling to the final size, the bonded layers are subjected to another heat treatment so that the layers are fused together so that they cannot be separated. In other embodiments, the first metal layer 108 is coated on the second metal layer 108 using any other suitable method.
    Figure 3 illustrates a cross-sectional view of an embodiment of a trimetallic strip (i.e., a clad trimetallic strip) 200b. The trimetallic strip 200b includes a first metal layer 108 and a second metal layer 107, as previously described and illustrated with reference to Figure 2, and a third metal layer 109. The third metal layer 109 and the first metal layer 108 are composed of different materials. In one embodiment, the third metal layer 1096 and the second metal layer 107 consist of the same material. In one embodiment, the third metal layer 109 consists of aluminum or an aluminum alloy. In other embodiments, the third metal layer 109 consists of silver, a silver alloy, palladium, a palladium alloy, or any other suitable metal. The third metal layer 109 has a thickness less than the thickness of the first metal layer 108 and the thickness of the second metal layer 107. In one embodiment, the third metal layer 109 has a thickness of between 1 μm and 0.1 mm. The third metal layer 109 is coated on the first metal layer 108 opposite the second metal layer 107 using a suitable method, such as the cladding process described previously with reference to Figure 2.
    Although the following Figures 4 to 13 illustrate the manufacture of a semiconductor device using the trimetallic strip 200b previously described and illustrated with reference to Figure 3, the illustrated process may also be applied to the bimetallic strip 200a previously described and illustrated by male reference to figure 2.
    Figure 4 illustrates a cross-sectional view of an embodiment of a base plate 210 that includes a cooling structure. The second metal layer 107 in the base plate 200b, which has been previously described and illustrated with reference to Figure 3, is structured to form a cooling structure with nal flanges or flanges 112 with spaces 114 between the nal flanges or flanges 112. The second metal layer 107 is deformed by cutting, punching or microdeforming technology (MDT) to give the second metal layer 106. MDT deforms the second metal layer 107 mechanically and plastically and forms nal flanges or flanges 112 without depositing any metal !.
    The second metal layer 107 is deformed in such a way that no part of the surface of the first metal layer 108 facing the second metal layer 106 is exposed. Because the surface has the first metal layer 108 not exposed, the first metal layer 108 is protected against corrosion. In one embodiment, nal flanges or flanges 112 are made by MDT, compression molding, or molding to provide nal flanges or flanges 112 with a length of 5.5 mm to 6 mm. In another embodiment, nal flanges or flanges 112 are fabricated by MDT to provide nal flanges or flanges 112 having a length d112 of 2 mm to 10 mm and gaps 114 having a width w115 of 1 to 10 mm. In another embodiment, squeegee flanges or flanges 112 are made by compression molding or die casting to give squeegee flanges or flanges 112 having a length d112 of 2 mm to 20 mm and gaps 114 having a width w115 of 1 mm to 20 mm. In other embodiments, nal flanges or flanges 112 are made to have other lamp lengths. Through a mold, hall 212 is cut or punched through the base plate 210 to mount the base plate 210 to other structures in the device, such as a chamber 102 to receive a coolant, as previously described and illustrated with reference to Figure 1. 7 As as illustrated in Figure 4, the second metal layer 106 may comprise a sublayer 113 which has no needles or no needles flanges 112. In a direction perpendicular to the spruce surface 168 between the first and second metal layers 108, 106 the sublayer 113 has a thickness d113. In one embodiment, the thickness d113 may be between 0.2 mm and 0.5 mm. Alternatively or in addition, the ratio between the thickness d108 of the first metal layer 108 and the thickness d113 of the sublayer 113 may be at least 4: 1 or at least 10: 1.
    In general, the material and thickness of the first metal layer 108 and the material, thickness and structure of the second metal layer 106 and the backsheet 113 can be selected so that the composite of the first metal layer 108 and the second metal layer 106, including the backsheet 113 and the squeegee flanges or flanges 112, in all directions parallel to the spruce surface 168 between the first and second metal layers 108, 106 have a CTE less than or equal to 18 ppm / K or even less than 17 ppm / K.
    Figure 5 illustrates a cross-sectional view of another embodiment of a base plate 220 that includes a cooling structure. The base plate 220 is similar to the base plate 210 previously described and illustrated with reference to Figure 4, except that the base plate 2 lacks a hollow 212 and that the third metal layer is structured to provide a third metal layer 110. Portions of the third metal layer 109 are etched. scraped, peeled off or deposited by any other method to expose portions 222 of the first metal layer 108 and to provide a third metal layer 110. The third metal layer 109 may be structured to provide the third metal layer 110 before or after the formation of nal flanges or flanges 112. In one embodiment, the first metal layer 108 comprises copper, and the structuring of the third metal layer prepares the base plate 220 for plating the first metal layer. In one embodiment, the third metal layer 110 comprises aluminum and provides a solder mask and a solder stop.
    Figure 6 illustrates a cross-sectional view of an embodiment of a substrate assembly 132a.
    The substrate assembly 132a includes metal-coated ceramic substrates 122 that include metal surfaces or layers 120 and 124, joints 126a and 126b, semiconductor chips 128a and 128b, and interconnecting wires 130. A first semiconductor chip 128a is attached to the metal layer 124 via a first joint 126a. A second semiconductor chip 128b is attached to the metal layer 124 via a second joint 126b. The joints 126a and 126b are soft-soldered joints, sintered joints, diffusion-soldered joints or other suitable joints.
    The semiconductor chips 128a and 128b are electrically coupled to the metal layer 124 via interconnecting wires 130. By means of a baffle. The connecting wires 1 comprise Al, Cu, Al-Mg, Au or some other suitable material. By an embodiment Or the interconnecting wires 130 are interconnected with the semiconductor chips 128a and 128b 8 and the metal layers 124 using ultrasonic bonding of wires. In other embodiments, clamps or copper strips and sintering are used to electrically couple the semiconductor chips 128a and 128b to the metal layer 124. Other substrate assemblies, such as the substrate assembly 132b previously described and illustrated with reference to Figure 1, may also be fabricated.
    Figure 7 illustrates a cross-sectional view of an embodiment of the substrate assemblies 132a and 132b joined to a base plate 104. The substrate assemblies 132a and 132b are joined to the first metal layer 108 via joints 118. In other embodiments, the substrate assemblies 132a and 132b are fabricated on a base plate 104. Embodiment soft solder the substrate assemblies 132a and 132b on the first metal layer 108 to provide lead joints 118. The solder joints 118 include Sn-Pb, Sn-Ag, Sn-Ag-Cu, Sn-Sb or any other suitable solder alloy. In one embodiment, the first metal layer 108 comprises copper or a copper alloy, and the third metal layer 110 comprises aluminum or an aluminum alloy and provides a solder mask and solder stop for the soldering process. In another embodiment, the diffusion solder substrate assemblies 132a and 132b on the first metal layer 108 to provide diffusion soldered joints 118. During the diffusion soldering process, soft solder is completely transferred to solid form to provide a pure intermetallic joint (eg, Cu3Sn, CuSSnSn). In another embodiment, the substrate assemblies 132a and 132b are sintered on the first metal layer 108 to provide sintered joints 118. Each sintered joint 118 is a sintered metal layer comprising sintered nanoparticles, such as Ag nanoparticles, Au nanoparticles, Cunanoparticles or other lamp nanoparticles. The substrate assembly 132a is electrically connected to the substrate assembly 132b via interconnecting wires 130.
    Figure 8 illustrates a cross-sectional view of another embodiment of the substrate assemblies 132a and 132b, joined to a base plate comprising a third metal layer 109. By this embodiment, the third metal layer 109 has not been structured to expose the first metal layer 108. The substrate assemblies 132a and 132b are soft, diffusion-soldered or sintered on the third metal layer 109 to give joints 242. In one embodiment, the third metal layer 109 comprises silver, a silver alloy, palladium or a palladium alloy. The third metal layer 109 may provide a spruce surface for sintering or diffusion soldering.
    Although the following Figures 9 to 13 include joints 118 joining the substrate assemblies 132a and 132b to the first metal layer 108, the embodiments may also be applied when joints 242 are used to join the substrate assemblies 132a and 132b to the third metal layer 109.
    Figure 9 illustrates a cross-sectional view of an embodiment of the substrate assemblies 132a and 132b, the base plate 104, the terminals 136 and a frame 134. The frame 134 is attached to the base plate 104 by screwing, gluing, clamping, soldering or some other suitable procedure. In one embodiment, the frame 134 contacts the upper surface of the third metal layer 110 and the side walls of the first metal layer 108, the second metal layer 106 and the third metal layer 110. In other embodiments (e.g., Figure 1), the frame 134 only contacts with the upper surface of the third metal layer 110 or the first metal layer 108 (i.e., if the third metal layer 110 is excluded).
    The terminals 136 are inserted into or formed by the frame 134 in such a way that a part of the terminals 136 extends outside the frame 134 for electrical power connections and control connections. A portion of the terminals 136 extends into the frame 134 for internal electrical connections to the substrate assemblies 132a and 132b. The terminals 136 are electrically connected to the substrate assemblies 132a and 132b via interconnecting wires 130. In other embodiments, the terminals 136 are electrically connected directly to the substrate assemblies 132a and 132b via soldering or any other suitable method.
    Figure 10 illustrates a cross-sectional view of an embodiment of the substrate assemblies 132a and 132b, the base plate 104, the terminals 136, the frame 134 and encapsulation material 138. Through one embodiment, a silicone gel is applied over the substrate assemblies 132a and 132b within the frame 134 to provide the enclosure 138 through other embodiments. the substrate assemblies 132a and 132b are coated with silicone, polyimide, epoxy or other suitable material to provide electrical insulation.
    Figure 11 illustrates a cross-sectional view of an embodiment of the substrate assemblies 132a and 132b, the base plate 104, the terminals 136, the frame 134, the encapsulation material 138 and a lid 140. Within one embodiment, a second encapsulation material, such as epoxy, is applied over the encapsulation material 138 to provide. In another embodiment, a tacking device is attached to the frame 134 by snapping, soldering, gluing or some other suitable procedure to provide the lid 140.
    Figure 12 illustrates a cross-sectional view of an embodiment of a semiconductor device 100 that includes a chamber 102 for receiving a coolant. The chamber 102 is fixed to the base plate 104 with screws 116. In other embodiments, the chamber 102 is fixed to the base plate 104 by gluing, soldering or some other suitable procedure. In one embodiment, the chamber 102 consists of aluminum or an aluminum alloy. In other embodiments, the chamber 102 consists of another suitable material, compatible with the coolant. The chamber 102 comprises an inlet and an outlet. In one embodiment, the chamber 102 conducts cooling water to hot areas in an optimal manner to compensate for small differences in the joining temperature for parallel or different semiconductor chips.
    Figure 13 illustrates a cross-sectional view of another embodiment of a semiconductor device 300 that includes a chamber 302 for receiving a coolant. By this embodiment, the chamber 302 is fabricated by laser thinning or gluing a thin metal layer onto the second metal layer 106 in the base plate 104. The thin metal layer is glued or laser glued to the second metal layer 106 at a plurality of points, as indicated, for example, at 304. the connection points 304 can be selected to adjust the pressure of and / or the flow of the coolant in the chamber. In one embodiment, the thin metal layer consists of aluminum or an aluminum alloy. In other forms of discharge, the thin metal layer consists of some other suitable material which is compatible with the cooling liquid. The semiconductor device 300 also includes hall 212 extending through the base plate 104 and the chamber 302. The shark 212 may be used to secure the semiconductor device 300 to another structure.
    Figure 14 illustrates a perspective view of another embodiment of a semiconductor device 320. In one embodiment, the semiconductor device 320 is a powerful power electronics module. The power electronics module 320 includes a base plate 322, a frame 324, power semiconductor chips 326, power terminals 328, 330 and 332 and control terminals 334. In one embodiment, the power terminals 228 are negative terminals, the power terminals 330 are positive terminals, and the power terminals 332 are terminal terminals.
    Terminals 238, 330, 332 and 334 are electrically connected to the power semiconductor chips 326 via interconnecting wires 336. Terminals 328, 330, 332 and 334 are indentation pins which all have the same mat, so that a single terminal type is used for all terminals in the power electronics module 320. Further stretchers The terminals 328, 330, 332 and 334 pass through the frame 324 around the periphery of the power electronics module 320. In one embodiment, the base plate 322 resembles the base plate 104 previously described and illustrated with reference to Figure 1.
    Figure 15 illustrates a perspective view of another embodiment of a semiconductor device 360. The semiconductor device 360 is similar to the semiconductor device 320 previously described and illustrated with reference to Figure 14, except that the semiconductor device 360 includes a cover 362 and the base plate 322 has been replaced. of the base plate 364. The lid 362 is a snap lid. The base plate 364 includes squeegee flanges 366. In one embodiment, the base plate 364 resembles the base plate 104 previously described and illustrated with reference to Figure 1.
    Figure 16 is a flow chart illustrating an embodiment of a method 400 for manufacturing a semiconductor device, such as the semiconductor device 100 previously described and illustrated with reference to Figures 1 and 12 or the semiconductor device 300 previously described and illustrated with reference to Figure 1; 13. At 402, a bimetallic or trimetallic strip is produced (ie, a clad strip) (eg, as previously described and illustrated with reference to Figures 2 and 3). At 404, the bottom layer of the clad strip is deformed to provide a base plate with a cooling structure with nal flanges or flanges (e.g., as previously described and illustrated with reference to Figure 4). At 406 11, substrates and semiconductor chips (e.g., substrate assemblies or separate components) are attached to the base plate (e.g., as previously described and illustrated with reference to Figure 7). At 408, the frame is assembled, encapsulation material is added and the package is closed (eg as previously described and illustrated with reference to Figures 9 to 11).
    At 410, a chamber is attached to receive a coolant at the base plate (e.g., as previously described and illustrated with reference to Figures 12 and 13).
    Embodiments provide a semiconductor device comprising a coated bimetal or trimetallic base plate comprising a cooling structure. The coated base plate provides an inexpensive solution for providing a base plate comprising a first metal layer, suitable for joining substrate assemblies, and a second metal layer, suitable for forming a cooling structure compatible with cooling water shoes. In addition, the connection between the coated layers is significantly stronger than that obtained with other techniques, such as cold gas spraying or bimetallic extrusion.
    Although specific embodiments have been elucidated and described, it will be appreciated by those skilled in the art that a number of alternative and / or corresponding implementations may replace the specific embodiments shown and described, without departing from the scope of the present description. This patent application is intended to thank all adaptations or variations of the specific embodiments discussed. The intention is thus that this description should be limited only by the claims and their equivalents. 12
    权利要求:
    Claims (35)
    [1] 1. l. A sen1iconductor device comprising:a semiconductor chip (l28) joined with a substrate ( 122);a base plate joined with the substrate (122), the base plate comprising a firstmetal layer ( 108) clad to a second metal layer (106), the second metal layer (106)deformed to provide a pin-fin or fin cooling structure (l 12), whereinthe second metal layer ( 106) comprises a sub-layer (l l3) that has nopins and no pin-fins;the first metal layer ( 108) comprises a first thickness (dl08);the sub-layer (l l3) comprises a second thickness (dl l3);the ratio between first thickness (dl08) and the second thickness(dl 13) is at least 4:1.
    [2] 2. The semiconductor device of claim l, wherein the ratio between first thickness (dl08) and the second thickness (dl l3) is at least l0:l.
    [3] 3. The semiconductor device of claim l or 2, wherein the second thickness (dl l3) is between 0.2 mm and 0.5 mm.
    [4] 4. The semiconductor device as claimed in one of the preceding claims,wherein the first metal layer (l08) comprises copper and the second metal layer ( 106) comprises alun1inum.
    [5] 5. The semiconductor device as claimed in one of the preceding claims,wherein the first metal layer (l08) has a thickness (dl08) between 2.5 mm and 10 IIIIII.
    [6] 6. The semiconductor device as claimed in one of the preceding claims, further comprising: 2011P50982SE/KR I9SCHIFT1543 SE/KR a third metal layer (109) clad to the first metal layer (108) opposite thesecond metal layer (106).
    [7] 7. The semiconductor device as claimed in claim 6, Wherein the third metal layer ( 109) has a thickness between 1 um and 0.1 mm.
    [8] 8. The semiconductor device as claimed in claim 6 or 7, Wherein the third metal layer (109) comprises one of silver and palladium.
    [9] 9. The semiconductor device as claimed in one of claims 6 to 8, Wherein thesubstrate (122) is one of diffusion soldered and sintered to the third metal layer (109).
    [10] 10. The semiconductor device as claimed in one of claims 6 to 9, Wherein the third metal layer (109) comprises alun1inum.
    [11] 11. The semiconductor device as claimed in claim 10, Whereinthe third metal layer (109) is structured to provide a solder stop layer; andWherein the substrate (122) is soldered to the first metal layer (108).
    [12] 12. The semiconductor device as claimed in one of the preceding claims,Wherein the first metal layer (108) and the second metal layer (106) including thesub-layer (113) and the pin-fins or fins (112) form a composite that has, in eachdirection parallel to an interface (168) between the first metal layer (108) and thesecond metal layer ( 106), at 20°C a coefficient of thermal expansion of less than or equal to 18 ppm/K or of less than 17 ppm/K.
    [13] 13. A sen1iconductor device comprising: a first metallized ceran1ic substrate ( 122); 2011P50982SE/KR I9SCHIFT1543 SE/KR a first sen1iconductor chip (128) joined with a first side of the first metallizedceramic substrate ( 122); anda base plate (104, 210, 220) joined with a second side of the first metallizedceramic substrate (122), the second side opposite the first side, the base plate ( 104,210, 220) comprising a first layer ( 108) comprising copper clad to a second layer(106) comprising alun1inum, the second layer deformed to provide a pin-fin or fincooling structure (112) , whereinthe second metal layer ( 106) comprises a sub-layer (113) that has nopins and no pin-fins;the first metal layer ( 108) comprises a first thickness (d108);the sub-layer (113) comprises a second thickness (d113); andthe ratio between first thickness (d108) and the second thickness(d113) is at least 4:1.
    [14] 14. The semiconductor device as claimed in claim 1, wherein the first metallayer (108) and the second metal layer ( 106) including the sub-layer (113) and thepin-fins or fins (112) form a composite that has, in each direction parallel to aninterface (168) between the first metal layer (108) and the second metal layer (106),at 20°C a coefficient of thermal expansion of less than or equal to 18 ppm/ K or of less than 17 ppm/K.
    [15] 15. The semiconductor device as claimed in one of claims 13 or 14, wherein the ratio between first thickness (d108) and the second thickness (d113) is at least 10:1.
    [16] 16. The semiconductor device as claimed in one of claims 13 to 15, wherein the second thickness (d113) is between 0.2 mm and 0.5 mm.
    [17] 17. The semiconductor device as claimed in one of claims 13 to 16, further comprising: 2011P50982SE/KR I9SCHIFT1543 SE/KR a second semiconductor (128) chip joined With the first side of the first metallized ceran1ic substrate ( 122).
    [18] 18. The semiconductor device as claimed in one of claims 16 or 17 Wherein thebase plate (104, 210, 220) is joined With a second side of the second metallized ceran1ic substrate (122), the second side opposite the first side.
    [19] 19. The semiconductor device as claimed in one of claims 16 to 18, furthercomprising: a chamber (102) for receiving a cooling fluid, the chamber ( 102) includingan inlet (142) and an outlet (144), the chamber (102) surrounding the coolingstructure; a frame (134, 324) attached to the base plate (104, 210, 220); potting surrounding the sen1iconductor chip (128) and the substrate (122); and a cap (140, 362) over the potting (138).20. The semiconductor device as claimed in one of claims 16 to 19, furthercomprising: a power terminal (328, 330, 332) electrically coupled to the firstsemiconductor chip ( 128); and a control terminal (334) electrically coupled to the first sen1iconductor chip(128),
    [20] 20. Wherein the power tern1inal (328, 330, 332) and the control tern1inal (334) have the same dimensions.
    [21] 21. A method for fabricating a sen1iconductor device, the method comprising:providing a cladded strip comprising a first metal layer (108) clad to a second metal layer ( 106); 2011P50982SE/KR I9SCHIFT1543 SE/KR structuring the second metal layer (106) to form a pin-fin or fin Coolingstructure (112); joining a sen1iconductor chip (128) with a substrate ( 122); andjoining the substrate (122) with the first metal layer ( 108); wherein the second metal layer ( 106) comprises a sub-layer (113) that has nopins and no pin-fins; the first metal layer ( 108) comprises a first thickness (d108); the sub-layer (113) comprises a second thickness (dl 13); and the ratio between first thickness (d108) and the second thickness(dl 13) is at least 4:1.
    [22] 22. The method as claimed in claim 21, wherein the first metal layer ( 108) andthe second metal layer (106) including the sub-layer (113) and the pin-fins or fins(112) form a composite that has, in each direction parallel to an interface (168)between the first metal layer (108) and the second metal layer ( 106), at 20°C acoefficient of thermal expansion of less than or equal to 18 ppm/ K or of less than 17 ppm/K.
    [23] 23. The method as claimed in 21 or 22, wherein the ratio between first thickness and the second thickness (d113) is at least 1031.
    [24] 24. The method as claimed in one of claims 21 to 23, wherein the second thickness (d113) is between 0.2 mm and 0.5 mm.
    [25] 25. The method as claimed in one of claims 21 to 24, wherein providing thecladded strip comprises providing the cladded strip comprising the first metal layer ( 108) comprising copper and the second metal layer (106) comprising aluminum. 2011P50982SE/KR I9SCHIFT1543 SE/KR
    [26] 26. The method as claimed in one of claims 21 to 25, wherein providing thecladded strip comprises providing the cladded strip comprising the first metal layer ( 108) having a thickness between 2.5 mm and 10 mm.
    [27] 27. The method as claimed in one of claims 21 to 26, wherein structuring thesecond metal layer (106) comprises one of stamping the second metal layer ( 106),cutting the second metal layer (106), and mechanically and plastically deforn1ing thesecond metal layer ( 106).
    [28] 28. A method for fabricating a sen1iconductor device, the method comprising:providing a cladded strip comprising a first metal layer (108) comprisingcopper clad to a second metal layer ( 106) comprising alun1inum;structuring the second metal layer (106) to form a pin-fin or fin coolingstructure;joining a sen1iconductor chip (128) with a first side of a metallized ceramicsubstrate (122);joining a second side of the metallized ceran1ic substrate (122) with the firstmetal layer (108), the second side opposite the first side; whereinthe second metal layer ( 106) comprises a sub-layer (113) that has nopins and no pin-fins;the first metal layer (108) comprises a first thickness (d108);the sub-layer comprises a second thickness (dl 13); andthe ratio between first thickness (d108) and the second thickness(dl 13) is at least 4:1.
    [29] 29. The method as claimed in claim 28, wherein the first metal layer (108) andthe second metal layer (106) including the sub-layer (113) and the pin-fins or fins(112) form a composite that has, in each direction parallel to an interface (168) between the first metal layer ( 108) and the second metal layer ( 106), at 20°C a 2011P50982SE/KR I9SCHIFT1543 SE/KR coefficient of thermal expansion of less than or equal to 18 pprn/ K or of less than 17 ppm/K.
    [30] 30. The method as claimed in claim 28 or 29, Wherein the ratio between first thickness (dl08) and the second thickness (dl 13) is at least 1031.
    [31] 31. The method as claimed in one of claims 28 to 30, Wherein the second thickness (dl 13) is between 0.2 mm and 0.5 mm.
    [32] 32. The method as claimed in one of claims 29 to 31, Wherein providing thecladded strip comprises at least one of providing the first metal layer (108)comprising a copper alloy and providing the second metal layer (106) comprising an aluminum alloy.
    [33] 33. The method as claimed in one of claims 29 to 32, Wherein providing thecladded strip comprises providing the cladded strip comprising a third metal layer (109) clad to the first metal layer ( 108) opposite the second metal layer ( 106).
    [34] 34. The method as claimed in claim 33, further comprising: structuring the third metal layer (109) to eXpose portions of the first metallayer (l08); and Wherein joining the second side of the metallized ceramic substrate (122)With the first metal layer (108) comprises soldering the second side of the metallized ceran1ic substrate ( 122) to the first metal layer ( 108).
    [35] 35. The method as claimed in claim 33 or 34, Wherein joining the second side ofthe metallized ceran1ic substrate (122) With the first metal layer (108) comprises oneof diffusion soldering and sintering the second side of the metallized ceran1ic substrate (122) to the third metal layer (109).
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    同族专利:
    公开号 | 公开日
    KR20130028866A|2013-03-20|
    US8519532B2|2013-08-27|
    KR101520997B1|2015-05-15|
    JP2013062506A|2013-04-04|
    JP5572678B2|2014-08-13|
    DE102012200325A1|2013-03-14|
    DE202012100090U1|2012-02-27|
    US20130062750A1|2013-03-14|
    SE1251008A1|2013-03-13|
    CN202454546U|2012-09-26|
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    法律状态:
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